iSTART-TEK and a Leading Domestic Memory Manufacturer Successfully Verified MTP BIST IP

iSTART-TEK announced that its self-developed MTP (Multiple-Time Programmable) BIST IP has been successfully verified in collaboration with a leading domestic memory manufacturing company, and has passed the functional verification on a real test chip. The verification results show that iSTART-TEK’s MTP BIST IP features high stability and flexible integration capability, and will be widely applied in various consumer electronic products in the future.
This verification was conducted using a 0.18 um logic process (1.8V/5V). The test chip includes a 16Kx16 main block and a 64x16x2 information block, with a total of 87 I/O pins. The MTP BIST IP uses a 5-pin JTAG interface to perform testing on the ATE platform, and supports the CP1 / CP2 test flow used in the manufacturing process, which can effectively detect potential defects in MTP memory cells. When the TF pin outputs 1’b1 during testing, a failure can be quickly identified, helping engineers to monitor yield conditions in real time.

At the system integration level, the MTP BIST IP allows adjustment of test flow parameters, flexibly supporting different SoC design requirements. It can also greatly shorten ATE test time and reduce test loading. Since MTP has the advantages of small area and low power consumption, when combined with iSTART-TEK’s BIST IP, it enables customers to easily complete comprehensive memory test verification at the SoC design stage, improving product quality and production efficiency.
iSTART-TEK stated that, in addition to the verified MTP BIST IP, the company’s complete NVM BIST IP product line, including eFlash BIST IP, has also been successfully verified on automotive and consumer IC platforms. The company expects these products to start contributing royalty revenue next year (2026), continuing to expand its market presence in the field of non-volatile memory testing.