In memory-centric SoC designs, a large number of small SRAM instances are often used. If each memory block carries its own dedicated TRA (Testing Redundancy Analyzer) control logic, it results in duplicated circuits, routing congestion, higher area overhead, and increased power consumption. To address these challenges, iSTART-TEK introduces the Repair Memory Wrapper, a design approach that allows multiple memories to share a unified repair control logic, greatly improving efficiency and reducing architectural complexity.
The core advantage of the Repair Memory Wrapper lies in grouping multiple small memories—with identical functions and sizes—into one consolidated repair module. By sharing a single TRA, the design eliminates redundant logic, reduces area and power, and maintains full repair testability, while improving overall manageability within the SoC.
Users simply configure the wrapper parameters inside the User-Defined Memory (UDM). Once the UDM is imported into the iSTART EDA platform, the system automatically generates all required repair logic—no manual coding needed—making the workflow more intuitive and less prone to errors. During TRA operation, the system identifies which memory requires repair based on the incoming address and automatically routes the correct repair address and repair enable information to the corresponding ports, ensuring a precise and reliable repair process.
As advanced process technologies continue to impose stricter constraints on area and power, the Repair Memory Wrapper provides a more compact, efficient, and scalable repair architecture. It helps customers enhance yield, control DPPM, and improve overall SoC quality and competitiveness—making it a key technology for modern memory-intensive designs.